Loop handling for single instruction multiple datapath processor architectures
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United States of America Patent
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May 4, 2004
Grant Date -
N/A
app pub date -
Nov 13, 2000
filing date -
Nov 13, 2000
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A method of controlling the enabling of processor datapaths in a SIMD processor during a loop processing operation is described. The information used by the method includes an allocation between the data items and a memory, a size of the array, and a number of remaining parallel passes of the datapaths in the loop processing operation. A computer instruction is also provided, which includes a loop handling instruction that specifies the enabling of one of a plurality of processor datapaths during processing an array of data items. The instruction includes a count field that specifies the number of remaining parallel loop passes to process the array and a count field that specifies the number of serial loop passes to process the array. Different instructions can be used to handle different allocations of passes to parallel datapaths. The instruction also uses information about the total number of datapaths.
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