Processor having a conditional branch extension of an instruction set architecture
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United States of America Patent
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May 4, 2004
Grant Date -
N/A
app pub date -
Jul 30, 1999
filing date -
Jul 30, 1999
priority date (Note) -
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Abstract
A processor having a conditional branch extension of an instruction set architecture which incorporates a set of high performance floating point operations. The instruction set architecture incorporates a variety of data formats including single precision and double precision data formats, as well as the paired-single data format that allows two simultaneous operations on a pair of operands. The extension includes instructions directed to branching if, for example, either one of two condition codes is false or true, if any of three condition codes are false or true, or if any one of four condition codes are false or true.
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