Clock template for configuring a programmable gate array
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United States of America Patent
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May 4, 2004
Grant Date -
N/A
app pub date -
Apr 26, 2001
filing date -
Apr 26, 2001
priority date (Note) -
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status (Latency Note)
Importance
Abstract
A clock template includes digital programming information for programming clock frames of a programmable gate array (PGA). The digital programming information represents a number of different clock configurations that correspond to various designs in the PGA. In one embodiment, the digital programming information includes a bit stream for partially reconfiguring the PGA. In another embodiment, the digital programming information is embedded in digital programming information of at least one of the designs. Methods of configuring a PGA with different designs having different clocking configurations by utilizing the clock template are also disclosed.
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