Micro grid array semiconductor die package

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 6734546
APP PUB NO 20030162319A1
SERIAL NO

10082174

Stats

ATTORNEY / AGENT: (SPONSORED)

Importance

Loading Importance Indicators... loading....

Abstract

See full text

A micro grid array semiconductor die package includes a housing defining a cavity for holding at least one semiconductor die, said housing including a plurality of insulative side walls, each of said side walls having a bottom surface and an interior wall including a top surface, and an end plate joined to said side walls; and a plurality of substantially straight conductive leads extending through at least one of said side walls, each of said conductive leads including an internal lead section extending into the cavity from the top surface of the interior wall and a external lead section extending externally from said at least one bottom surface of said side wall.

Loading the Abstract Image... loading....

First Claim

See full text

Family

Loading Family data... loading....

Patent Owner(s)

Patent OwnerAddress
SILICON BANDWIDTH INC46539 FREMONT BOULEVARD FREMONT CA 94538

International Classification(s)

  • [Classification Symbol]
  • [Patents Count]

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Alcaria, Vicente D Richmond, CA 4 38
Crane, Jr Stanford W Santa Clara, CA 66 1288
Jeon, Myoung-Soo Fremont, CA 16 203

Cited Art Landscape

Load Citation

Patent Citation Ranking

Forward Cite Landscape

Load Citation