Method and apparatus for self-referenced wafer stage positional error mapping
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United States of America Patent
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-
May 11, 2004
Grant Date -
Aug 8, 2002
app pub date -
Jun 26, 2001
filing date -
Dec 8, 2000
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A wafer stage overlay error map is created using standard overlay targets and a special numerical algorithm. A reticle including a 2-dimensional array of standard overlay targets is exposed several times onto a photoresist coated silicon wafer using a photolithographic exposure tool. After exposure, the overlay targets are measured for placement error using a conventional overlay metrology tool. The resulting overlay error data is then supplied to a software program that generates a 2-dimensional wafer stage distortion and yaw overlay error map.
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