Method and apparatus to facilitate global routing for an integrated circuit layout
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United States of America Patent
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May 11, 2004
Grant Date -
Dec 11, 2003
app pub date -
Jun 6, 2002
filing date -
Jun 6, 2002
priority date (Note) -
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status (Latency Note)
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Abstract
A system that facilitates generating a global routing for a layout of an integrated circuit operates by receiving a netlist to be routed. The system partitions this netlist into global signals, datapath signals, and control signals. Next, the system creates a tiling grid of the integrated circuit and routes connection nets between tiles within this grid. The system then selects an area within the integrated circuit larger than a tile in the first grid. The system creates a second grid of tiles smaller than the tiles of the first grid within this selected area. During this process, connection nets are routed between tiles on the second grid while routings within the first grid are maintained. The system merges connection nets within the first grid with connection nets within the second grid to form the global routing.
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