Tri-directional, high-speed bus switch
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United States of America Patent
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-
May 18, 2004
Grant Date -
Aug 1, 2002
app pub date -
Jan 29, 2002
filing date -
Feb 1, 2001
priority date (Note) -
In Force
status (Latency Note)
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Abstract
A tri-directional, high-speed switching element connects to a bus port, an A memory port, and a B memory port. A first FET switch' source is connected to the bus port, and a second FET switch's drain is connected to the A memory port, and its source is connected to the first FET switch's drain. A third FET switch's drain is connected to the B memory port, and its source is connected to the second FET switch's drain. This element permits all three ports to be isolated from each other, or for the A and B ports to be interconnected, but isolated from the bus port, or for all ports to be connected together. A collection of 8 such switching elements is provided on a single silicon chip, providing switching for a byte of interleaved memory.
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