Method and apparatus for generating impedance matched output signals for an integrated circuit device
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United States of America Patent
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May 18, 2004
Grant Date -
N/A
app pub date -
May 1, 2003
filing date -
May 1, 2003
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
An apparatus for generated impedance matched output signals for an integrated circuit is disclosed. The apparatus includes a master true driver circuit, a master complement driver circuit and multiple clone output driver circuits. The master true driver circuit includes a first driver control, a first output driver, a first impedance matching resistor and a first load. The master complement driver circuit includes a second driver control, a second output driver, a second impedance matching resistor and a second load. The clone output driver circuits, which are substantially identical to each other, can produce impedance matched output signals to their respective substantially identical loads. Each of the clone output driver circuit includes a driver control, a first unity gain amplifier, a second unity gain amplifier and a load. The inputs to the first and second unity gain amplifiers are supplied by the master true circuit and the master complement circuit via the driver control.
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