Frame synchronization circuit
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United States of America Patent
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May 18, 2004
Grant Date -
Oct 9, 2003
app pub date -
Oct 13, 1998
filing date -
Feb 13, 1997
priority date (Note) -
Expired
status (Latency Note)
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Abstract
In a frame synchronization circuit, which prevents the occurrence of synchronous error due to a data loss/insertion while restraining a false synchronization/out of synchronization based on typical code error in a conventional data transmission system, the frame synchronization circuit is provided with a frame synchronization code detector which detects a frame synchronization code from a received data sequence to output a frame position and outputs a checked result by checking a frame synchronization code detected and a correct frame synchronization code. The frame synchronization circuit is also provided with and a data loss and data insertion period judgment circuit which determines which presumes whether a data loss or data insertion has occurred in the received data sequence according to the checked result.
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