Scalable efficient I/O port protocol

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United States of America Patent

PATENT NO 6738836
SERIAL NO

09652391

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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A system that supports a high performance, scalable, and efficient I/O port protocol to connect to I/O devices is disclosed. A distributed multiprocessing computer system contains a number of processors each coupled to an I/O bridge ASIC implementing the I/O port protocol. One or more I/O devices are coupled to the I/O bridge ASIC, each I/O device capable of accessing machine resources in the computer system by transmitting and receiving message packets. Machine resources in the computer system include data blocks, registers and interrupt queues. Each processor in the computer system is coupled to a memory module capable of storing data blocks shared between the processors. Coherence of the shared data blocks in this shared memory system is maintained using a directory based coherence protocol. Coherence of data blocks transferred during I/O device read and write accesses is maintained using the same coherence protocol as for the memory system. Data blocks transferred during an I/O device read or write access may be buffered in a cache by the I/O bridge ASIC only if the I/O bridge ASIC has exclusive copies of the data blocks. The I/O bridge ASIC includes a DMA device that supports both in-order and out-of-order DMA read and write streams of data blocks. An in-order stream of reads of data blocks performed by the DMA device always results in the DMA device receiving coherent data blocks that do not have to be written back to the memory module.

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Patent Owner(s)

  • HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Duncan, Samuel H Arlington, MA 44 550
Hartwell, David W Bolton, MA 22 580
Kessler, Richard E Shrewsbury, MA 127 4343
Lang, Steve Stow, MA 17 519
Webb, Jr David A J Groton, MA 4 155

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