Controller architecture and strategy for small discontiguous accesses to high-density memory devices
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United States of America Patent
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May 18, 2004
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N/A
app pub date -
Feb 16, 2002
filing date -
May 2, 2001
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Abstract
A RAM device including a memory and a memory controller. The memory controller can be configured to buffer incoming requests, prioritize the requests into a final order, and submit the requests to the memory in the final order. The final order, as needed, is selected to maximize overlap of incoming requests' timing cycles.
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