Error correction circuit and error correction method
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
May 18, 2004
Grant Date -
Oct 17, 2002
app pub date -
May 13, 1999
filing date -
May 13, 1998
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
The present invention provides an error correction circuit for receiving and decoding a trellis-encoded signal of a series of data Z.sub.q, Z.sub.q-1, . . . ,Z.sub.1 which comprises convolutional-encoded bits and unencoded bits, the convolutional-encoded bits being obtained by convolutional-encoding lower t bits X.sub.t, X.sub.t-1, . . . ,X.sub.1 of an input p-bit series of data X.sub.p, X.sub.p-1, . . . , X.sub.1 (where p.gtoreq.2, q.gtoreq.p, and p>t.gtoreq.1), and the unencoded bits being obtained by not convolutional-encoding upper (p-t) bits thereof. The circuit includes: a maximum likelihood decoder for preselecting one of m parallel paths of transition from state x at time k to state y at time k+1.
First Claim
Family
International Classification(s)
- [Classification Symbol]
- [Patents Count]
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully