Method for phase locking in a phase lock loop
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United States of America Patent
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Jun 1, 2004
Grant Date -
N/A
app pub date -
Aug 30, 2001
filing date -
Aug 30, 2001
priority date (Note) -
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status (Latency Note)
Importance
Abstract
An apparatus comprising a phase lock loop (PLL) and a lock circuit. The PLL may be configured to multiply an input frequency in response to a lock signal. The lock circuit may be configured to generate the lock signal. The PLL may also be configured to select a reference frequency as (i) the input frequency when in a first mode and (ii) a divided frequency of the input frequency when in a second mode.
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