Importance

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Abstract

A dual-bit floating-gate flash cell structure comprises a gate region being formed between a common-source region and a common-drain region. The gate region comprises a pair of floating-gates being defined by a pair of second sidewall dielectric spacers and a select-gate dielectric layer being formed between the pair of floating-gates. The common-source/drain region comprises a common-source/drain diffusion region or a pair of isolated source/drain diffusion regions being divided by a shallow trench isolation formed between a pair of first sidewall dielectric spacers. A word line being formed over an intergate dielectric layer is at least formed over the pair of floating-gates and the select-gate dielectric layer. Based on common-source/drain diffusion regions and isolated source/drain diffusion regions of the dual-bit floating-gate cell structure, two different contactless flash memory arrays are formed.

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First Claim