EEPROM erasing method
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United States of America Patent
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Jun 1, 2004
Grant Date -
Oct 31, 2002
app pub date -
Apr 10, 2002
filing date -
Sep 14, 1990
priority date (Note) -
Expired
status (Latency Note)
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Abstract
An electrically erasable programmable read-only memory cell array has a plurality of memory cells supplied with a supply voltage and a ground voltage. Each memory cell has a storage transistor with a floating gate. For each of selected memory cells, a first voltage higher than both the supply voltage and the ground voltage is applied to the control gate of the storage transistor and a second voltage lower than both the supply voltage and the ground voltage is applied to one of the source/drain electrodes of the storage transistor to thereby erase data in all of the selected memory cells.
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