Data pipeline timing optimization technique in a multi-port bridge for a local area network

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United States of America Patent

PATENT NO 6744728
SERIAL NO

09273134

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Abstract

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A method of optimizing a data path in a multi-port bridge for a local area network (LAN) includes steps of: identifying a data path through the multi-port bridge wherein the data path includes a plurality of stages in a serial arrangement, wherein each stage performs a corresponding operation on data received from the LAN by the multi-port bridge; identifying a stage in the data path wherein the identified stage requires a period of time to perform its corresponding operation which is longer than any other stage; and subdividing the identified stage into two or more subdivided stages wherein the operations performed by the subdivided stages collectively perform the operation associated with the identified stage and wherein each of the two or more subdivided stages requires a period of time to perform its corresponding operation which is shorter than the period of time required for the identified stage to perform its corresponding operation. The method can include determining a bandwidth required for the multi-port bridge; and determining a frequency for a clock signal based upon the bandwidth. The method can also include repeatedly subdividing selected stages until a slowest stage in the data path is operable according to the clock signal. The invention results in a beneficial trade-off in which bandwidth for the multi-port bridge and latency are both increased.

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Patent Owner(s)

Patent OwnerAddress
SONY CORPORATION1-7-1 KONAN MINATO-KU TOKYO 108-0075
SONY ELECTRONICS INC1 SONY DRIVE PARK RIDGE NJ 07656

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Chung, David Sunnyvale, CA 38 996

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