Raid system having multiple reply queues for use with multiprocessor host
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United States of America Patent
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Jun 1, 2004
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N/A
app pub date -
Aug 22, 2000
filing date -
Aug 22, 2000
priority date (Note) -
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Abstract
An SMP computing system has a RAID controller and an interconnect bus system for communication processors and the RAID controller. There are in host memory a plurality of reply queues, at least one of which is associated with each processor of the SMP computing system. Replies associated with commands originating from a first processor are buffered by the RAID controller in a first reply queue, and replies associated with commands originating from a second processor are buffered in a second reply queue.
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