Bus architecture for system on a chip
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United States of America Patent
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Jun 1, 2004
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N/A
app pub date -
Sep 22, 2000
filing date -
Jun 12, 2000
priority date (Note) -
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Abstract
A multiple bus architecture for a system on a chip including bridges for decoupling clock frequencies of individual bus masters from peripherals they are accessing. Each bridge interfaces to all bus masters in the system that require access to the peripherals it interfaces to.
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