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Abstract

In a multithreaded processor, a method and an apparatus to selectively disable one or more threads is disclosed. As multithreading is increasingly becoming the normative paradigm of computer architecture, there still may instances which warrant disabling a thread, such as using operating systems not coded for the specific number of threads, having defective registers/arrays peculiar to a thread, certain kinds of testing procedures. Thus a method is disclosed to test the function of each thread separately and discern if any threads have defective register/arrays. If so or for other reasons, a method and apparatus are disclosed to selectively disable access to the registers/arrays peculiar to the thread. Features of the invention allow the disablement of individual storage elements in multithreaded registers/arrays or to disable access to hardware registers or individual bits in hardware registers associated with the failed thread. Techniques can be used to route data and instructions for the disabled thread to other threads. Preferably, the tests are performed and the method to disable access to the register/arrays are accomplished before the processors are sold.

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First Claim