Importance

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Abstract

A field programmable gate array comprising a plurality of logic modules each logic module having two clusters, said logic modules arranged in rows and columns. The logic module clusters having a plurality of receiver components, a plurality of transmitter components, at least one buffer module, and at least one sequential logic components. Each logic module also comprises at least one left combinatorial logic unit having a carry-in input and carry-out output and at least one right combinatorial logic unit having a carry-in input and carry-out output adjacent to said left combinatorial logic unit. The carry-out output of the left combinatorial unit is hardwired to the carry-in input of said right combinatorial logic unit providing dedicated carry-in/carry-out logic circuitry.

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First Claim