Programmable logic devices with multi-standard byte synchronization and channel alignment for communication
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United States of America Patent
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Jun 15, 2004
Grant Date -
Mar 20, 2003
app pub date -
Jul 11, 2002
filing date -
Sep 17, 2001
priority date (Note) -
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status (Latency Note)
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Abstract
A programmable logic device ('PLD') includes communication interface circuitry that can support any of a wide range of communication protocols, including Packet Over Sonet ('POS-5') and 8-bit/10-bit ('8B10B') protocols. The interface circuitry includes various functional blocks that are at least partly hard-wired to perform particular types of functions, but that in at least many cases are also partly programmable to allow the basic functions to be adapted for various protocols. Routing of signals to, from, between, and/or around the various functional blocks is also preferably at least partly programmable to facilitate combining the functional blocks in various ways to support various protocols.
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