High density memory cell
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United States of America Patent
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Jun 15, 2004
Issued Date -
N/A
app pub date -
Aug 26, 2002
filing date -
Mar 3, 2000
priority date (Note) -
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Abstract
A memory cell comprising an inverting stage, an access transistor coupled between a data line and an input of the inverting stage, the access transistor being responsive to a control signal for selectively coupling the data line and the inverting stage input, a feedback transistor coupled to the inverting stage input and being responsive to an output of the inverting stage for latching the inerting stage in a first logic state and whereby the cell is maintained in a second logic state by a leakage current flowing through the access transistor which is greater than a current flowing through the feedback transistor.
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