Flash memory array architecture
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United States of America Patent
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Jun 15, 2004
Grant Date -
Mar 20, 2003
app pub date -
Aug 27, 2002
filing date -
Aug 29, 2001
priority date (Note) -
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status (Latency Note)
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Abstract
A flash memory array architecture. In one embodiment, a flash memory device comprises a first and second bank. Each bank has a pair of quadrants of memory cells. Each quadrant has a redundant fuse circuit to store operating parameters. Moreover, each redundant fuse circuit is coupled within an associated quadrant to reduce routing of signal lines. Each quadrant further has a sense amplifier circuit to read the memory cells.
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