Test pattern compression method, apparatus, system and storage medium
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United States of America Patent
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Jun 15, 2004
Grant Date -
N/A
app pub date -
Sep 28, 2000
filing date -
Sep 29, 1999
priority date (Note) -
Expired
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Abstract
A system and method for test pattern compression includes a local CPU for dividing faults into a plurality of fault groups, assigning the fault groups to respective remote CPUs, that are connected to the local CPU in parallel with each other. Each remote CPU generates test patterns having undefined values assigned to pins of the logic circuit that do not participate in fault detection. The local CPU acquires pluralities of test patterns of the remote CPUs, generates new test patterns obtained by merging those test patterns that have identical pattern numbers among the pluralities of test patterns, and attempts to merge these newly generated test patterns.
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