Test point monitor using embedded passive resistance
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United States of America Patent
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Jun 22, 2004
Issued Date -
N/A
app pub date -
Dec 23, 2002
filing date -
Dec 23, 2002
priority date (Note) -
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status (Latency Note)
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Abstract
Exemplary techniques for providing a test point in a printed circuit board (PCB) or other circuit device that minimizes or eliminates intrusive effects in the transmitted as well as the monitored data signal are disclosed. A deposited resistor is used to provide a connection between a signal electrode and a transmission line of the PCB. Where the transmission line is embedded, the PCB may also include a tap to connect the signal layer of the PCB (having the embedded transmission line) with the signal electrode at the surface layer of the PCB. The deposited resistor is intended to act as a voltage-divider resistor and to buffer any perturbations of the system resulting from the tap and the introduction of a probe. Additionally, the deposited resistor may be positioned relative to the transmission line as to provide a equalization capacitance to compensate for parasitic capacitance.
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