Shared memory control between detector framing node and processor
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United States of America Patent
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Jun 22, 2004
Grant Date -
Feb 13, 2003
app pub date -
Jan 31, 2001
filing date -
Jan 31, 2001
priority date (Note) -
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Abstract
An imaging system shares control of host memory between a detector framing node and a host processor. The detector framing node is programmable to control generation and reception of image data. Image data is acquired and communicated to host memory independently from control by a host operating system. The detector framing node controls events according to an event instruction sequence and communicates received image data to the host memory through a computer communication bus. Image data is received by the detector framing node from a flat panel detector. Host memory has a first section managed by the host operating system and a second section not managed by the host operating system. Image data is communicated from the detector framing node into the second section of host memory. Event instruction sequences are communicated from the first section of host memory to the detector framing node to control the generation and reception of image data.
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