External resistor and method to minimize power dissipation in DC holding circuitry for a communication system
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United States of America Patent
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Jun 22, 2004
Grant Date -
Feb 14, 2002
app pub date -
Oct 9, 2001
filing date -
Apr 22, 1997
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A CMOS implementation for a DC holding circuit in direct access arrangement (DAA) circuitry is disclosed that provides desirable inductive behavior while minimizing power dissipation required by the CMOS integrated circuit, particularly at high loop currents. The DC holding circuitry disclosed may include MOS transistors located on a CMOS integrated circuit and an off-chip power dissipating resistor that acts to dissipate power external to the CMOS integrated circuit. The CMOS implementation disclosed also allows a path for drawing DC current to power other CMOS circuits (e.g. ADCs and DACs) in the CMOS integrated circuit.
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