Flexible FIFO system for interfacing between datapaths of variable length
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United States of America Patent
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Jun 22, 2004
Issued Date -
N/A
app pub date -
May 10, 2001
filing date -
May 10, 2001
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A FIFO buffer arrangement is disclosed that is capable of buffering and transferring data between multiple input and output datapaths of varying widths. All of the input and output buses may be used to transfer data concurrently. Data that are written to the FIFO via any of the input buses may be extracted from the FIFO via any of the output buses. The FIFO efficiently carries out all necessary width conversions when performing the data transfers.
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