Memory array with read/write methods
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United States of America Patent
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Jun 22, 2004
Issued Date -
N/A
app pub date -
Mar 23, 2000
filing date -
Jul 5, 1994
priority date (Note) -
Expired
status (Latency Note)
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Abstract
Improved circuitry for connecting the memory array to a data bus allows for high speed accessing of the memory array. Sense amplifier latches are coupled to each column of memory cells. The latched sense amplifiers are coupled to decoders which, in turn, are coupled to data amplifiers. The data amplifiers are coupled to a data bus. Data being read from or written to the memory cells is via the sense amplifier latches, the decoders, and data amplifiers.
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