Gaining access to internal nodes in a PLD

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 6754862
SERIAL NO

09802480

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ATTORNEY / AGENT: (SPONSORED)

Importance

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Abstract

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Internal registers of a PLD are exposed for debugging using a JTAG port and a scan chain. The user of a PLD identifies registers at the source code level. These registers are automatically inserted in a scan chain. An EDA software tool provides a means of choosing a register from the electronic design. The EDA tool connects the selected register to the JTAG scan chain and passes information to the software about the location in the scan chain. The EDA tool provides for scanning of the chain under automatic or manual control. The selected nodes are extracted from the chain and displayed in a user-specified format. Registers in encrypted blocks are exposed. The vendor of the block decides which registers are of importance. Once selected, the vendor creates a 'debugging' file which is delivered to the customer along with the encrypted block. The debugging file contains the names of the registers, their data type, and their symbolic values.

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Patent Owner(s)

  • ALTERA CORPORATION

International Classification(s)

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Fairman, Michael C Santa Cruz, CA 4 71
Hoyer, Bryan H Boulder Creek, CA 4 90

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