Process for manufacturing multiple layer wiring substrate onto which thin film capacitor is incorporated
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United States of America Patent
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-
Jun 29, 2004
Grant Date -
May 15, 2003
app pub date -
Nov 12, 2002
filing date -
Nov 12, 2001
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A process facilitates manufacturing a multiple layer wiring board having therein a thin-film capacitor The process includes: forming a metallic film layer having a barrier metal layer and a metal layer to be sequentially anode oxidized on an insulating layer first conductor pattern; covering a lower electrode forming region of the thin film capacitor in the first conductor pattern with a first resist film; etching to remove an uncovered portion of the metallic film layer; removing the first resist film and covering the first conductor pattern, except for part of the metallic film layer, with a second resist film; forming an anodic oxidation film on the exposed metallic film layer; removing the second resist film and attaching an adherence layer and a metal seed layer, sequentially, on the anodic oxidation film end on the first conductor pattern; and forming an upper electrode second conductor pattern on the anodic oxidation film.
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