Apparatus and technique for maintaining order among requests issued over an external bus of an intermediate network node
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United States of America Patent
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Jun 29, 2004
Grant Date -
N/A
app pub date -
May 17, 2001
filing date -
May 17, 2001
priority date (Note) -
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Abstract
An apparatus and technique off-loads responsibility for maintaining order among requests issued over a split transaction bus from a processor to a split transaction bus controller, thereby increasing the performance of the processor. A logic circuit enables the controller to defer issuing a subsequent (write) request directed to an address on the bus until all pending (read) requests complete. By off-loading responsibility for maintaining order among requests from the processor to the controller, the invention enhances performance of the processor since the processor may proceed with program execution without having to stall to ensure such ordering. The logic circuit maintains the order of the requests in an efficient manner that is transparent to the processor.
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