Semiconductor package including stacked chips with aligned input/output pads
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United States of America Patent
Stats
-
Jul 6, 2004
Grant Date -
Jan 2, 2003
app pub date -
Mar 23, 2001
filing date -
Mar 25, 2000
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
Semiconductor packages are disclosed. An exemplary package includes horizontal leads each having a first side and an opposite second side. The second side includes a recessed horizontal surface. Two stacked semiconductor chips are within the package and are electrically interconnected in a flip chip style. One chip extends over the first side of the leads and is electrically connected thereto. The chips are encapsulated in a package body formed of an encapsulating material. The recessed horizontal surface of the leads is covered by the encapsulating material, and a portion of the second side of each lead is exposed at an exterior surface of the package body as an input/output terminal. A surface of one or both chips may be exposed. The stack of chips may be supported on the first side of the leads or on a chip mounting plate.
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