Data latch circuit having anti-fuse elements
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United States of America Patent
Stats
-
Jul 6, 2004
Grant Date -
Dec 18, 2003
app pub date -
Jun 16, 2003
filing date -
Jun 14, 2002
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A data latch circuit includes anti-fuse elements for storing remedy information therein as to replacement of defective memory cells by redundant memory cells. For programming the anti-fuse elements to a logic level '1' in a programming mode, control signals CTL1 and CTL2 are set at a low level and a high level, respectively, and programming control signals PGMA and PGMB are set at a high level and a low level, respectively. A voltage selection node Nvs delivers a programming voltage Vpp, lowering an output terminal RCB to effect dielectric breakdown of anti-fuse element 25, which assumes a low resistance. In a normal operation mode, programming voltages PUMA and PGMB are set at a low level and a high level, respectively, and both control signals CTL1 and CTL2 are set at a low level Voltage output node Nvs delivers the normal operating voltage, raising output terminal RC to a high level to thereby deliver the stored logic level '1'.
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- Non-US Classification not provided for expired patents
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- Citation Ranking not provided for expired patents
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