Device for timing reconstruction of a data channel transported on a packet network and its process
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United States of America Patent
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Jul 6, 2004
Grant Date -
N/A
app pub date -
Jun 20, 2000
filing date -
Jun 22, 1999
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Abstract
A memory for data accumulation includes an input on which such data are entered as a stream of input data under the control of an input timing signal and an output starting from which the data entered in memory are read as a stream of output data under the control of a reconstructed timing signal. A phase-locked loop uses this input timing signal as an input signal to generate a corresponding phase-locked output signal. Of such phase-locked loop output. A device is provided to measure residual phase wander and act on the transfer function band of the phase of phase-locked loop output which is preferably without ring filters.
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