Integrated circuits with scalable design
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United States of America Patent
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Jul 6, 2004
Grant Date -
Jun 5, 2003
app pub date -
Dec 3, 2001
filing date -
Dec 3, 2001
priority date (Note) -
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Abstract
A method for designing at least one mask for manufacturing an integrated circuit is disclosed. The method may include generating a schematic; entering data representing transistors of the set into a computer-aided design system; identifying transistors expected to be subject to voltage levels beyond the bounds of a power rail and a ground rail; designating robust geometries such transistors and operating the computer-aided design system to generate mask or masks. Integrated circuits of scalable design are also disclosed.
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