Semiconductor memory device having a circuit for fast operation
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United States of America Patent
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Jul 13, 2004
Issued Date -
N/A
app pub date -
May 23, 2003
filing date -
Jun 28, 1999
priority date (Note) -
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Abstract
A semiconductor memory device includes a command decoder receiving an external signal and issuing a command, a clock buffer receiving an external clock, gates and a refresh counter. When a test signal is at L-level, an auto-refresh signal is issued in accordance with the output of the command decoder. When the test signal is at H-level, the auto-refresh signal is issued in accordance with the output (external clock) of the clock buffer. Thereby, the test can be performed with a good timing accuracy even by a low-speed tester.
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