Data coherent logic for an SRAM device
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United States of America Patent
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Jul 13, 2004
Grant Date -
Jun 17, 2004
app pub date -
Dec 17, 2002
filing date -
Dec 17, 2002
priority date (Note) -
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Abstract
The present invention provides data coherent logic for an SRAM device. The present invention utilizes a data strobe signal and an output strobe signal to control data written into and read out of the. SRAM device from an input/output pad. Data coherent logic is designed to resolve timing conflicts between the data and output strobe signals. The logic selectively delays the output strobe signal when a match occurs for data requested in a read operation immediately following a write operation. The delay allows sufficient time for the data to be registered and selected before being outputted from the device.
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