Importance

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Abstract

A method and system of providing access to a shared memory interconnected to a first controller and a second controller via a bus, the bus having control signals associated therewith for data transfer control and communication between the first and the second controllers. The second controller transmits an access request to the first controller for control of the bus to access the memory. The first controller selectively grants the access request and transmits an acknowledge to the second controller; and upon receiving the acknowledge, the second controller accesses the memory for data transfer. The first controller has a first priority for accessing the memory, and the second controller has a second priority for accessing the memory, the second priority being lower than the first priority such that upon request the first controller selectively grants control of the bus to the second controller for memory access, otherwise the first controller maintains control of the bus for memory access. In one embodiment, the second controller transmits an access request to the first controller for control of the bus to access the memory; and in response, the first controller selectively grants the access request and transmits an acknowledge to the second controller. Each of the controllers relinquishes control of the bus by placing the bus in tristate, wherein the relinquishing controller stops driving the bus.

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First Claim