Method of manufacturing a scalable flash EEPROM memory cell with floating gate spacer wrapped by control gate
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Jul 20, 2004
Issued Date -
N/A
app pub date -
Jul 9, 2003
filing date -
Nov 6, 2001
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A scalable flash EEPROM cell having a semiconductor substrate with a drain and a source and a channel therebetween. A select gate is positioned over a portion of the channel and is insulated therefrom. A floating gate is a spacer having a bottom surface positioned over a second portion of the channel and is insulated therefrom. The floating gate has two side surfaces extending from the bottom surface. A control gate is over the floating gate and includes a first portion that is adjacent the floating gate first side surface, and a second portion adjacent the floating gate second side surface.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully