Method and arrangement for layout and manufacture of gridded non manhattan semiconductor integrated circuits
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United States of America Patent
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Jul 27, 2004
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N/A
app pub date -
Oct 5, 2001
filing date -
Jun 3, 2001
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Abstract
The present invention introduces several methods for implementing non Manhattan routing systems for integrated circuit manufacture. In one embodiment, a non Manhattan routing system is implemented by memorizing where intersections between wiring pitch grids occur and connecting such intersections with vias. In another embodiment, a gridless non Manhattan routing systems may be implemented by adapting a gridless Manhattan routing system by rotating a plane of a tile based maze router.
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