Access delay test circuit for self-refreshing DRAM
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United States of America Patent
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Aug 3, 2004
Grant Date -
N/A
app pub date -
Sep 11, 2002
filing date -
Sep 11, 2002
priority date (Note) -
Expired
status (Latency Note)
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Abstract
An enhanced arbitration and control subsystem for a self-refreshing DRAM has a normal mode of operation and a test mode of operation in which an internal refresh cycle is automatically performed prior to each external access cycle. A first gate is opened in a normal mode of operation to enable internal refresh cycles upon receipt of an internal refresh request signal. The first gate is closed in a test mode to disable any internal refresh requests. A second gate is opened in the test mode of operation to provide a path for an external access request signal to first trigger initiation of an internal refresh cycle prior to an external access cycle. The second gate is closed in a normal mode of operation to allow normal arbitration between internal refresh request signals and external RAS request signals.
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