Method and apparatus for invalidating a cache line without data return in a multi-node architecture
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United States of America Patent
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Aug 3, 2004
Grant Date -
Jun 20, 2002
app pub date -
Dec 20, 2000
filing date -
Dec 20, 2000
priority date (Note) -
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status (Latency Note)
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Abstract
A method of invalidating a cache line in a system having a plurality of nodes that include a processor and a cache memory. A request to invalidate a cache line that is caching a particular memory block is sent from a first node. The request is a request to invalidate a cache line in another node without returning to the first node the data stored in a cache line to be invalidated. In an embodiment, the data in the cache line to be invalidated is not returned to the first node even if the cache line is in the modified state. In a further embodiment, new data is written to a cache line in the first node that is caching the particular memory block without writing old data that was stored in that cache line back to a memory.
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