Insertable block tile for interconnecting to a device embedded in an integrated circuit
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United States of America Patent
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Aug 3, 2004
Grant Date -
N/A
app pub date -
Jun 13, 2002
filing date -
Jun 13, 2002
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
Method and apparatus for an insertable block tile is described. More particularly, a reserved area in an integrated circuit layout is removed, and terminated conductive line information is extracted from a layout database affected by the removal. The terminated conductive line information is used to create extensions or pins of the conductive lines terminated, as well as to identify signals associated with those terminated conductive lines. These physical or layout names and coordinates are mapped and then translated to logic names and coordinates for placement and routing to create the insertable block tile.
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