System and method for testing multiple embedded memories
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United States of America Patent
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Aug 10, 2004
Grant Date -
N/A
app pub date -
Apr 1, 2003
filing date -
Apr 1, 2003
priority date (Note) -
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Abstract
The present invention provides a system and method for testing embedded memories. The present invention logically combines many different embedded memories into one or more large, virtual memory blocks in order to test multiple memories together. The invention defines the X and/or Y address space in all memories in order to cover all memories combined. Compare circuits associated with each memory module are used to compare the data output from each memory cell to an expected value (e.g., to a value that would be expected if the memory cell was operating properly). The invention further uses mask logic to 'mask out' any unimplemented address space in each individual memory. The mask logic will always indicate that the comparison or memory test passed when unimplemented addresses are selected. The results of the comparison may be bundled and multiplexed to a test input/output port.
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