Low-power CMOS flip-flop
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United States of America Patent
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Aug 17, 2004
Grant Date -
Oct 9, 2003
app pub date -
Apr 3, 2003
filing date -
Apr 4, 2002
priority date (Note) -
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Abstract
A flip-flop includes a charge storage area that stores a logic voltage indicating a logic state of the flip-flop, a first transistor having a source or drain connected to a clock signal generating circuit, a second transistor having a source or drain connected to the clock signal generating circuit, a clock signal generated by the clock signal generating circuit that is ramped or sinusoidal, and a latching circuit that latches a latch voltage value based on voltages at the first transistor and the second transistor. The charge storage area supplies a first voltage representing a state of the storage voltage to a gate of the first transistor and supplies a second voltage to a gate of the second transistor.
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