Display operation with inserted block clears
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United States of America Patent
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Aug 17, 2004
Grant Date -
Jan 31, 2002
app pub date -
Jul 31, 2001
filing date -
Jul 31, 2000
priority date (Note) -
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status (Latency Note)
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Abstract
An SLM PWM clocking method, called 'jog clear,' for generating short bit periods where block data clears (74) are inserted between block data loads (72, 76) within a frame refresh period. The method significantly reduces the short bit duration that requires use of the earlier reset-release method and it eliminates undesirable artifacts present in these earlier SLM clocking methods.
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