Memory architecture for TCCT-based memory cells
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United States of America Patent
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Aug 17, 2004
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N/A
app pub date -
Jun 12, 2002
filing date -
Jun 12, 2002
priority date (Note) -
Expired
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Abstract
A memory architecture especially adapted to provide an architecture to house one or more TCCT-based memory cells and to provide a reference signal. The memory architecture is designed to effectively resolve stored information from memory cells into logical values, such as logical '0' and '1.' An exemplary memory architecture includes a data block that comprises a first set of one or more bit lines, where a word line one line extends to a first subset of the first set of the one or more bit lines. The data block also includes a word line two line extending to a second subset of the first set of the one or more bit lines. A memory cell is coupled to the word line one line, the word line two line and a common bit line of the first and second subsets of bit lines.
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