Data processor capable of executing an instruction that makes a cache memory ineffective
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United States of America Patent
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-
Aug 17, 2004
Issued Date -
N/A
app pub date -
Jun 22, 2001
filing date -
Mar 15, 1985
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A data processor formed on a LSI chip has an instruction address generator, an instruction cache memory having entries each storing an instruction address and an instruction corresponding to the instruction address, an instruction decoder decoding an instruction from said cache memory corresponding to an instruction address from said instruction address generator, an operand address generator generating an operand address in response to an output signal of said instruction decoder, and an operand cache memory having entries each storing an operand address and operand data corresponding to the operand address in its entry. The data processor executes an instruction that makes entries in both of said instruction cache memory and said operand cache memory ineffective.
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