Failsafe differential amplifier circuit
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United States of America Patent
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Aug 24, 2004
Grant Date -
May 13, 2004
app pub date -
Nov 12, 2002
filing date -
Nov 12, 2002
priority date (Note) -
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status (Latency Note)
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Abstract
Differential input fail safe circuitry is disclosed that detects missing or too low differential signals combined with a frequency lower than a frequency limit where a final safe condition is detected and signaled. The output signal form the fail safe circuitry is held in a given state that is an invalid representation of the differential input signal. A frequency detector, complementary offsetting auxiliary amplifiers with limit frequency roll offs are used to detect the fail safe condition. In addition a delay circuit is used that requires the fail safe condition to exist for some time before the fail safe circuit is active. Initialization circuitry ensures a proper power up conditions where the circuitry is enabled to detect the fail safe conditions and guarantees a reliable fail safe irrespective of the previous state of the signal.
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